1. Field of the Invention
This invention relates to a semiconductor memory device and a method of making the same. More particularly, this invention relates to a semiconductor memory device having a stacked cell structure wherein element regions are isolated by a field shield element isolation structure, and a method of making the same.
2. Description of the Related Art
Prior art DRAMs having a stacked cell structure have widely employed a cell layout shown in FIG. 12 which conforms with a folded bit line system capable of offsetting noises between bit lines.
This conventional DRAM will be explained with reference to FIGS. 12 through 14. Incidentally, the element isolation in this example is effected by a field shield element isolation system.
FIG. 12 is a schematic plan view showing layout of the DRAM, FIG. 13 is a sectional view taken along a line XIII--XIII of FIG. 12, and FIG. 14 is a sectional view taken along a line XIV-XIV of FIG. 12.
As shown in FIGS. 12 through 14, a field shield element isolation structure 101 is formed on a P-type silicon substrate 112, and gate electrode wirings 103 of memory cells that constitute word lines and gate electrodes 110 of peripheral transistors are formed in the element regions isolated by this field shield element isolation structure 101 by gate oxide films 113, respectively. Drain and source diffusion layers 102 and 119 are so formed as to interpose the gate electrode wiring 103 between them and pad polycrystalline silicon films 104 and 118, which have been used as impurity diffusion sources of the drain and source diffusion layers 102, 119, are formed on their surfaces, respectively.
As shown in FIGS. 13 and 14, the drain diffusion layer 102 of each memory cell is connected to a storage electrode 106 through the pad polycrystalline silicon film 104 and a storage contact 105, and a capacitor insulating film 111 and a cell plate electrode 109 are formed successively on the storage electrode 106.
On the other hand, the source diffusion layer 119 is common to two gate electrode wirings 103 or two memory cells, as shown in FIG. 13, and is connected to a bit line 108 formed above a cell plate electrode 109 through the pad polycrystalline silicon film 118 and a bit contact 107.
As shown in FIG. 12, the bit contacts 107 are disposed at every other bit lines 108 in a direction extending along the word line 103 (the direction indicated by an arrow A) and are disposed at an interval corresponding to four word lines 103 in the direction extending along the bit line 108 (the direction indicated by an arrow B).
The storage contacts 105 are aligned in the direction of the word line 103 in accordance with this arrangement of the bit contacts 107 as shown in FIGS. 12 and 14. In the direction of the bit line 108, on the other hand, there are disposed the bit contacts 107, the storage contacts 105, the field shield element isolation structures 101 and the adjacent storage contacts 105 in that order.
According to this construction, the space for increasing the cell capacity by expanding the surface area of the storage electrode 106 formed immediately above the storage contact 105 no longer exists substantially.
Therefore, the height of the storage electrode 106 has been increased in recent years in order to secure a sufficient cell capacitance in accordance with shrinkage of the cell size. As a result, an aspect ratio of the bit contact 107 becomes greater as shown in FIG. 13, and it has become difficult to form a wiring of aluminum or the like by a conventional sputtering process. Therefore, a polycide structure which is stable for process such as thermal treatment has been used for the bit line 108 in place of the aluminum wiring.
Particularly when the field shield element isolation system is used, the height of the element isolation region becomes more than double in comparison with a conventional LOCOS process, and the use of the polycide structure for the bit line 108 becomes essential.
In the prior art cell layout described above, there is no way but to increase the height of the storage electrode 106 in order to secure a sufficient cell capacitance. As a result, the aspect ratio of the bit contact 107 becomes great, and a buried plug technology using a polycide wiring, polycrystalline silicon or tungsten has been employed so as to secure connection reliability.
However, only an N type impurity can be doped to a polycrystalline silicon layer used for the polycide wiring and for this reason, the polycide wiring can be applied only to the wiring connected to only the bit contact 107 and peripheral N-type conductive layers.
Further, the buried plug using polycrystalline silicon can be applied only to the bit contact 107 and the peripheral N type conductive layers.
In the case of the buried plug using tungsten which can be connected to conductive layers of both conductivity types, on the other hand, TiN (titanium nitride), which is used as a barrier metal and a glue layer CVD-tungsten as formed by CVD, is formed by sputtering. Therefore, connection reliability is low in the contact having a high aspect ratio.
In order to reduce as much as possible the aspect ratio of the peripheral contacts 120, the existing process forms a step at a boundary portion between a cell array portion and a peripheral portion by using BPSG (Boro-Phospho Silicate Glass) reflow thereby to reduce the thickness of an inter layer insulating film 115 of the peripheral portion.
However, as the cell size has been reduced more and more in recent years, the height of the storage electrode 106 has become much higher and the step at the boundary between the cell array portion and the peripheral portion becomes much greater. On the other hand, the margin of depth of focus, at which a very small size can be precisely focused in photolithography, has become smaller for the bit line 108 disposed in each cell pitch. As a result, the problem that the bit line 108 extending from the cell array portion to the peripheral portion has a reduced accuracy in dimension due to poor resolution at the step between them has become serious in practice.